A.D.A. Amiga Demoscene Archive

Hi everyone,

in this thread: http://eab.abime.net/showthread.php?t=34481 -- a fellow was wondering about where and how memory overlap cycles appear on the 68030.

I speculated a bit there, and performed some measurements on Blizzard 1260. (Results can be found in the attached .pdf in the original thread). The speculations apply to the 68060 if datacache and Store Buffer is disabled, but does not apply 100% if Store Buffer is enabled. Is there someone who can explain why I'm seeing the behaviour I am?

Specifically, why the following code:



... which is graphed on the first page... has an initial step, but then increases linearly (with no 14-cycle-high staircasing)? I would really have expected that to staircase a bit with the Store Buffer enabled.

Datacache reads on the 030 are not free(0 cycles). I guess all ram axxess will halt the pipeline. On 060 I assume the move from fastram will pipeline only if the data in (a0) is in the cash.

.loop
move.l d3,(a1)+ ;chip
move.l (a0)+,d0 ;fast
subq.l #1,d7
bne.s .loop

In my Microbotics 50mhz 030 card I can pipeline 10 or 11 addx in your loop above. (and still maintain copyspeed).

.loop move.l (fastmem),d0 ;2 cycles of this instruction can be pipelined after the chipmem write
move.l d1,(chipmem)
REPT 11
addx.l d2,d2 ;22 cycles.
ENDR
dbf d7,.loop ;4 cycles